Transistor and its method of manufacture

ABSTRACT

A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.

FIELD OF THE INVENTION

The present invention relates to transistors and their methods ofmanufacture, and in particular, although not exclusively, to thin filmfield effect transistors.

BACKGROUND TO THE INVENTION

Field effect transistors comprising source and drain terminals, and agate terminal to which a voltage can be applied to control theconductivity of a semiconductive channel connecting the source and drainterminals are well known in a variety of particular forms. Typically, adielectric material is arranged between the gate terminal and thechannel of semiconductive material, and this dielectric material oftentakes the form of a layer of dielectric material which also covers thesource and drain terminals. A known problem with such transistors istheir parasitic capacitance resulting from the proximity of the gateterminal to the source and drain terminals (with dielectric materialbetween them). This parasitic capacitance results in lower switchingspeeds and higher losses (for example in the form of higher heatdissipation). The parasitic capacitance, and hence these problems,increase if the gate terminal overlaps the source and/or drainterminals. Indeed, generally speaking, the greater the amount of overlapbetween the gate terminals and the source and drain terminals, thegreater the parasitic capacitance and the related problems.

To reduce or minimise parasitic capacitance, it is desirable tomanufacture the transistor such that the gate terminal is confined tocovering just the semiconductive channel, and does not overlap eitherthe source or drain terminals. However, how to achieve this accuratealignment is a technical problem.

For certain applications, there is motivation to use dielectric materialhaving relatively high dielectric constant as the gate dielectric. Forexample, use of such high dielectric constant material (also known ashigh K material) can enable the dielectric layer to be made thinner,enabling thin film transistors to be constructed. However, the use ofhigh K material can exacerbate the parasitic capacitance problem. Forthe same amount of overlap between the gate and source terminals, forexample, the higher the dielectric constant of the dielectric materialbetween them, the greater the parasitic capacitance will be (assumingall other factors are the same).

Thus, the motivation to use high K material as the gate dielectric inthin film transistors conflicts with the desire to reduce parasiticcapacitance.

SUMMARY OF THE INVENTION

It is an aim of certain aspects and embodiments of the present inventionto provide transistors, and methods of manufacturing transistors, whichovercome, at least partially, one or more of the problems associatedwith the prior art.

According to a first aspect of the present invention there is provided atransistor comprising:

-   -   a layer (or other body) of semiconductor material comprising a        first portion, a second portion, and a third portion connecting        the first portion to the second portion and providing a        semiconductive channel between the first portion and the second        portion;    -   a conductive first terminal (e.g. a source terminal) covering        and in electrical contact with said first portion of the layer        of semiconductor material;    -   a conductive second terminal (e.g. drain terminal) covering and        in electrical contact with said second portion of the layer of        semiconductor material;    -   a conductive gate terminal comprising a first overlapping        portion covering at least part of the first terminal, and a        channel portion covering the third portion of the layer of        semiconductor material; and    -   a layer (or other body) of a first dielectric material, having a        first dielectric constant, arranged between the first        overlapping portion and the first terminal, and between the        channel portion of the gate terminal and the third portion of        the layer of semiconductor material,    -   characterised in that the transistor further comprises a layer        (or other body) of a second dielectric material having a second        dielectric constant, said second dielectric constant being lower        than said first dielectric constant, said layer of said second        dielectric material being arranged between at least part of the        first overlapping portion and the first terminal,    -   whereby said at least part of the first overlapping portion of        the gate terminal is separated from the first terminal by said        layer of first dielectric material and said layer of second        dielectric material.

Advantageously, therefore, by arranging the layer or other body of thesecond dielectric material between at least part of the firstoverlapping portion of the gate and the first terminal, the parasiticcapacitance associated with that overlap is reduced compared with thevalue it would have were the second dielectric material not present(i.e. if the overlapping portion of the gate and the first terminal wereseparated only by the first dielectric material).

In certain embodiments, the second dielectric material is a low-Kmaterial, that is a material with a small dielectric constant relativeto silicon dioxide. The dielectric constant of silicon dioxide istypically about 3.9 or 4. Thus, in certain embodiments the seconddielectric constant may be 4, lower than 4, for example lower than 3.9,such as 3.5, 3.0, 2.0, or even lower. Generally, the lower thedielectric constant of the second dielectric material, the lower theparasitic capacitance of the transistor for a given geometry (i.e. aparticular overlapping configuration of gate with respect to sourceand/or drain terminals and separation between the gate and underlyingterminal or terminals).

In certain embodiments, said layer (or other body) of said seconddielectric material is arranged to separate all of the first overlappingportion of the gate terminal from the first terminal. This helpsminimise the parasitic capacitance resulting from the overlap. However,in certain alternative embodiments the layer or other body of seconddielectric material may be arranged to cover just a portion (i.e. notall) of the first terminal.

In certain embodiments the layer or other body of second dielectricmaterial may be arranged to cover all of the first terminal. Again, thishelps minimise parasitic capacitance for a given amount of overlapbetween the gate and first terminal.

In certain embodiments the layer or other body of second dielectricmaterial is arranged directly in contact with the first terminal (forexample the second dielectric material may be formed directly on anupper surface of the first terminal). However, in alternativeembodiments this arrangement is not essential, and in general the layeror other body of second dielectric material may be arranged at anyposition between the overlapping portion of gate and the underlyingterminal, for example above or below the first dielectric material, orembedded within it, and may still achieve the desired effect of reducingparasitic capacitance compared with the situation were the seconddielectric material not present.

In certain embodiments, the gate terminal comprises a second overlappingportion covering at least part of the second terminal, and said layer offirst dielectric material is further arranged between the secondoverlapping portion and said second terminal.

In such embodiments, said layer (or other body) of said seconddielectric material is further arranged between at least part of thesecond overlapping portion and the second terminal, whereby said atleast part of the second overlapping portion of the gate terminal isseparated from the second terminal by said layer of first dielectricmaterial and said layer of second dielectric material.

Thus, by arranging the relatively low K dielectric material underneatheach of the overlapping portions of the gate, the parasitic capacitanceof the transistor is further reduced. In such embodiments, theseportions of second dielectric material are portions of a common layer orother body of the second dielectric material. In alternativeembodiments, rather than these portions of second dielectric materialbeing portions of a common layer or body, they may be provided byseparate layers or bodies, not connected to one another.

Thus, in certain embodiments the transistor may further comprise afurther layer (or other body) of said second dielectric material,wherein said further layer of said second dielectric material isarranged between at least part of the second overlapping portion and thesecond terminal, whereby said at least part of the second overlappingportion of the gate terminal is separated from the second terminal bysaid layer of first dielectric material and said further layer of seconddielectric material. Just the same as when the two portions of seconddielectric material were provided by a common layer or body, in theseembodiments there is still second dielectric material underneath eachoverlapping portion of the gate, and again parasitic capacitance isreduced.

In certain embodiments, said layer or further layer of said seconddielectric material is arranged to separate all of the secondoverlapping portion of the gate terminal from the second terminal.Again, this helps further reduce or minimise parasitic capacitanceresulting from overlap.

In certain embodiments, said layer or further layer of said seconddielectric material is arranged to cover all of the second terminal.Again, this helps reduce parasitic capacitance.

In certain embodiments the layer or further layer of second dielectricmaterial is arranged in contact with the second terminal, for exampledirectly on an upper surface of that second terminal. However, inalternative embodiments the layer or further layer of second dielectricmaterial may be arranged at any position between the overlaying secondportion of the gate and the underlying second terminal, and will stillprovide the advantage of reducing parasitic capacitance.

In certain embodiments, said layer of said second dielectric materialdoes not overlap said third portion of the layer of semiconductormaterial.

This can help increase or maximise the electrostatic coupling betweenthe gate terminal and the third portion of the layer of semiconductormaterial (i.e. the channel portion).

In certain embodiments, the first dielectric material may have adielectric constant of around 3.9 or 4. In alternative embodiments, thefirst dielectric material may be a high-K material, that is a materialhaving a dielectric constant higher than 4. Advantageously, the layer orbody of first dielectric material can be made relative thin, whilst thepresence of the second dielectric material maintains a low parasiticcapacitance for the device overall.

In certain embodiments the second dielectric material may be one of:benzocyclobutene, polyimide, parylene, organic silicate polymer.

Another aspect of the present invention provides a method ofmanufacturing a transistor comprising a layer (or other body) ofsemiconductor material comprising a first portion, a second portion, anda third portion connecting the first portion to the second portion andproviding a semiconductive channel between the first portion and thesecond portion, the method comprising:

-   -   forming said layer (or other body) of semiconductor material;    -   forming a layer (or other body) of conductive material over        (covering) said layer of semiconductor material;    -   forming a layer (or other body) of a second dielectric material        (e.g. low-K material), having a second dielectric constant, over        (covering) the layer of conductive material;    -   patterning the layers of conductive material and second        dielectric material to expose (uncover) said third portion of        the layer of semiconductor material, leave a first portion of        the layer of conductive material covering the first portion of        the layer of semiconductor material, leave a first portion of        the layer of second dielectric material covering at least part        of the first portion of the layer of conductive material, leave        a second portion of the layer of conductive material covering        the second portion of the layer of semiconductor material, and        leave a second portion of the layer of second dielectric        material covering at least part of the second portion of the        layer of conductive material, the first and second portions of        the layer of conductive material providing a source terminal and        a drain terminal respectively;    -   forming a layer (or other body) of a first dielectric material,        having a first dielectric constant, over the first and second        portions of the layer of second dielectric material and over the        exposed third portion of the layer of semiconductor material,        said second dielectric constant being lower than said first        dielectric constant; and    -   forming a further layer (or other body) of conductive material        over at least a portion of the layer of first dielectric        material covering said third portion of the layer of        semiconductor material to provide a gate terminal to which a        potential may be applied to control a conductivity of the        semiconductive channel.

Advantageously, by forming the layer or other body of second dielectricmaterial and then patterning the layers of the conductive material andsecond dielectric material before forming the further layer or otherbody of conductive material to form a gate, this technique ensures thatoverlapping portions of the gate are separated from the source and drainterminal by second dielectric material as well as first dielectricmaterial, and hence parasitic capacitance of the eventual transistor isreduced compared with an arrangement in which the second dielectricmaterial were not present. Also, by forming the transistor in this way,the precise positioning of the gate relative to the source and drainterminals is less important, in the sense that overlap can be toleratedwhile still providing low parasitic capacitance, compared with prior arttechniques where very accurate alignment was required in order tominimise overlap between the gate and underlying source and drainterminals to try to minimise parasitic capacitance.

In certain embodiments, said patterning of the layers of conductivematerial and second dielectric material comprises using a first mask(e.g. a gate mask).

In certain embodiments, said further layer of conductive materialcomprises at least one overlapping portion covering at least part of atleast one of the source and drain terminals.

In certain embodiments, the further layer of conductive materialcomprises a first overlapping portion covering at least part of one ofthe source and drain terminals, and a second overlapping portioncovering at least part of the other one of the source and drainterminals.

In certain embodiments, the further layer of conductive material coversthe first, second, and third portions of the layer of semiconductormaterial.

In certain embodiments, the method further comprises patterning thefurther layer of conductive material. In such embodiments, thepatterning of the further layer of conductive material may compriseusing a second mask (e.g. a via mask).

In certain alternative embodiments, said forming of the further layer ofconductive material comprises printing (e.g. selective printing) thefurther layer of conductive material.

In certain embodiments, said layer of conductor material furthercomprises a further portion extending from one of the first and secondportions of the layer of conductor material.

In certain embodiments, said layer of a second dielectric materialcomprises a further portion covering said further portion of the layerof conductive material, said layer of a first dielectric materialcomprises a further portion covering said further portion of the layerof a second dielectric material, and the method further comprises:

-   -   patterning the layers of first dielectric material and second        dielectric material to expose (uncover) at least part of the        further portion of the layer of conductive material.

In certain embodiments, said further layer of conductive materialcomprises a further portion in contact with said at least part of thefurther portion of the layer of conductive material.

Certain transistors embodying the invention may further comprise atleast one support layer (or other body) arranged to support the layer ofsemiconductor material. The at least one support layer or other body maycomprise at least one of: an insulator; a barrier; a substrate; and acarrier.

In certain methods embodying the invention, the method may furthercomprise forming or providing at least one support layer (or other body)to support the layer of semiconductor material.

According to another aspect of the invention there is provided atransistor comprising:

a layer of semiconductor material comprising a first portion, a secondportion, and a third portion connecting the first portion to the secondportion and providing a semiconductive channel between the first portionand the second portion;

a conductive source terminal arranged over and in contact with saidfirst portion of the layer of semiconductor material;

a conductive drain terminal arranged over and in contact with saidsecond portion of the layer of semiconductor material;

a layer of a first dielectric material, having a first dielectricconstant, arranged over at least a portion of the source terminal, overand in contact with the third portion of the layer of semiconductormaterial, and over at least a portion of the drain terminal; and

a conductive gate terminal arranged over and in contact with said layerof said first dielectric material and extending over said third portionof the layer of semiconductor material and extending over said portionof the source terminal and said portion of the drain terminal,characterised in that the transistor further comprises a layer of asecond dielectric material having a second dielectric constant, saidsecond dielectric constant being lower than said first dielectricconstant, arranged over at least one of said portion of the sourceterminal and said portion of the drain terminal, between said layer ofsaid first dielectric material and at least one of said portion of thesource terminal and said portion of the drain terminal.

Another aspect of the invention provides a method of manufacturing atransistor comprising a layer of semiconductor material comprising afirst portion, a second portion, and a third portion connecting thefirst portion to the second portion and providing a semiconductivechannel between the first portion and the second portion, the methodcomprising:

-   -   forming said layer of semiconductor material;    -   forming a layer of conductive material over said layer of        semiconductor material;    -   forming a layer of a second dielectric material, having a second        dielectric constant, over the layer of conductive material;    -   patterning the layers of conductive material and second        dielectric material to expose (uncover) said third portion of        the layer of semiconductor material, leave a first portion of        the layer of conductive material and a first portion of the        layer of second dielectric material covering the first portion        of the layer of semiconductor material, and leave a second        portion of the layer of conductive material and a second portion        of the layer of second dielectric material covering the second        portion of the layer of semiconductor material, the first and        second portions of the layer of conductive material providing a        source terminal and a drain terminal respectively;    -   forming a layer of a first dielectric material, having a first        dielectric constant, over the first and second portions of the        layer of second dielectric material and over the exposed third        portion of the layer of semiconductor material, said second        dielectric constant being lower than said first dielectric        constant; and    -   forming a layer of conductive material over at least a portion        of the layer of first dielectric material covering said third        portion of the layer of semiconductor material to provide a gate        terminal to which a potential may be applied to control a        conductivity of the semiconductive channel.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described withreference to the accompanying drawings, of which:

FIG. 1 is a schematic representation of a transistor embodying theinvention;

FIG. 2 is a schematic representation of another transistor embodying theinvention;

FIG. 3 illustrates steps A-O in a method of manufacturing a transistorin accordance with the present invention;

FIG. 4 illustrates steps A-C in the patterning of a layer in certainmethods embodying the invention;

FIG. 5 illustrates alternative steps A-C suitable for patterning layersin embodiments of the present invention;

FIG. 6 illustrates another transistor embodying the invention;

FIG. 7 illustrates part of an electronic circuit embodying the inventionand incorporating a transistor embodying the invention;

FIG. 8 illustrates another transistor embodying the invention; and

FIG. 9 illustrates another transistor embodying the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Referring now to FIG. 1, this illustrates a transistor 100 embodying theinvention. The transistor 100 comprises: a layer (or other body) ofsemiconductor material 1 comprising a first portion 11, a second portion12, and a third portion 13 connecting the first portion to the secondportion and providing a semiconductive channel between the first portionand the second portion; a conductive first terminal 21 (e.g. a sourceterminal) covering and in electrical contact with said first portion ofthe layer of semiconductor material; a conductive second terminal 22(e.g. drain terminal) covering and in electrical contact with saidsecond portion of the layer of semiconductor material; a conductive gateterminal 50 comprising a first overlapping portion 51 covering at leastpart of the first terminal 21, and a channel portion 53 covering thethird portion 13 of the layer of semiconductor material; and a layer (orother body) of a first dielectric material 4, having a first dielectricconstant, arranged between the first overlapping portion 51 and thefirst terminal, and between the channel portion 53 of the gate terminaland the third portion 13 of the layer of semiconductor material.

The transistor further comprises a layer (or other body) 31 of a seconddielectric material 3 having a second dielectric constant, said seconddielectric constant being lower than said first dielectric constant,said layer of said second dielectric material being arranged between atleast part of the first overlapping portion and the first terminal.Thus, said at least part of the first overlapping portion of the gateterminal is separated from the first terminal by said layer of firstdielectric material and said layer of second dielectric material.

In this embodiment, the first overlapping portion 51 of the gate coversall of the underlying first terminal 21 and the channel portion 53 ofthe gate 50 covers all of the underlying semiconductive channel 13. Thegate 50 does not, in this embodiment, overlap the second terminal 22. Inthis example the layer or other body 31 of a second dielectric materialis embedded in the portion 41 of the layer or other body of the firstdielectric material 4. That layer or other body of second dielectricmaterial 31 does not, in this example, cover the entire first terminal21, but covers the majority of it. Thus, the presence of that layer orbody 31 substantially reduces the parasitic capacitance which, at leastin part, results from the position of the overlapping portion 51 of thegate above the first terminal 21. In alternative embodiments, however,the layer or body 31 may be arranged differently, and may cover theentire portion of the first terminal overlapped by the gate 50, as willbe appreciated from the description of the embodiments below.

Referring now to FIG. 2, this illustrates another transistor 100embodying the invention. In this embodiment the layer or body ofsemiconductor material 1 is supported by a multi-layer supportstructure, in this example comprising a carrier 6, a substrate 7, abarrier layer 8, and an insulator layer 9. The layer of semiconductormaterial 1 has been formed on the upper surface of the insulator layer 9and again comprises a first portion 11, a second portion 12, and a thirdportion 13. Source and drain terminals, 21 and 22 respectively, areformed on the first and second portions of the semiconductor layer, 11,12, and in turn are, in this example, completely covered by first andsecond portions 31, 32 respectfully of a layer of low K material. Thus,the low K material completely covers each of the source and drainterminals. The layer or body 4 of first dielectric material is formedover the underlying structure, such that a first portion 41 covers thelow K dielectric body 31, a second portion 42 covers the low Kdielectric body 32, a third portion 43 covers the channel portion 13,and further portions 40 cover the insulator layer. The gate terminal 50is formed on top, and comprises a channel portion 53 covering thesemiconductor channel 13, a first overlapping portion 51 overlapping aportion of the source terminal but being separated from the sourceterminal by 41 and 31, and a second overlapping portion 52 overlappingpart of the drain terminal 22, but again being separated from that drainterminal by both low K dielectric material 32 and first dielectricmaterial 42.

A method suitable for manufacturing the transistor shown in FIG. 2 (thatmethod also embodying the invention) is as follows:

(i) Prepare substrate 7 on carrier 6

(ii) Deposit barrier 8 (optionally)

(iii) Deposit insulator 9

(iv) Deposit semiconductor 1 (and optionally pattern)

(v) Deposit source-drain electrode layer 2

(vi) Deposit low-k dielectric layer 3

(vii) Pattern low-k dielectric layer 3 (to form regions/bodies 31 and32)

(viii) Pattern source-drain electrode layer 2 (using patterned low-Klayer as mask) to form source and drain terminals 21, 22

(ix) Deposit gate dielectric layer 4

(x) Pattern gate dielectric layer (optional)

(xi) Pattern low-k dielectric layer (optional)

(xii) Deposit gate layer 5

(xiii) Pattern gate layer 5

The optional second patterning of the low-k dielectric layer can use thegate dielectric layer (if patterned) as a hard-mask (if an appropriatematerial is chosen). The optional second step of patterning the low-kdielectric material creates a via to the SD (source-drain) electrodelayer which can be used to connect to the gate electrode layer at thenext stage.

It will be appreciated that in the transistor of FIG. 2 the gatepartially overlaps both terminals 21, 22. However, each of theoverlapping portions 51 and 52 is separated from the respectiveunderlying terminal by low-k material, hence parasitic capacitance iskept low.

With regard to materials, the substrate may be flexible, and thesubstrate may be formed from a material selected from a list comprising:glass (rigid or flexible); polymer (e.g. polyethylene naphthalate orpolyethylene terephthalate); polymeric foil; paper; insulator coatedmetal (e.g. coated stainless-steel); cellulose; polymethyl methacrylate;polycarbonate, polyvinylalcohol; polyvinyl acetate; polyvinylpyrrolidone; polyvinylphenol; polyvinyl chloride; polystyrene;polyethylene naphthalate; polyethylene terephthalate; polyimide (e.g.Nylon); poly(hydroxyether); polyurethane; polycarbonate; polysulfone;polyarylate; polyetheretherketone (PEEK); acrylonitrile butadienestyrene; 1-Methoxy-2-propyl acetate (SU-8); polyhydroxybenzylsilsesquioxane (HSQ); polyimide; parylene; Benzocyclobutene (BCB);Al2O3, SiOxNy; SiO2; Si3N4; spin-on glass; UV-curable resin; Nanoimprintresist; photoresist.

Barrier may be a planarization layer, for example a UV curable polymer,spin-on glass, polyimide, BCB, SU8.

Insulator may be organic or inorganic, and is chosen to match theproperties of the semiconductor layer. For example, a metal-oxideinsulating material may be used to match a metal-oxide semiconductor.Such materials include SiO2, Al2O3, Ta2O5, HfO2, SiNx, which may bedeposited by processes such as PVD, CVD or ALD, or using solutionprocesses such as sol-gel, spray pyrolysis.

The semiconductor material may be n-type or p-type, and could beinorganic or organic. Examples of metal-oxide semiconductor materialsinclude zinc oxide, tin oxide, cuprous oxide, nickel oxide. Otherinorganic semiconductor such as amorphous, microcrystalline ornanocrystalline silicon; binary metal oxides such as zinc tin oxide,indium tin oxide, indium zinc oxide; ternary metal oxides such asGaInZnO; metal oxynitrides e.g. ZnxOyNz; organic or polymersemiconductors. Newer semiconductor materials such as 2D electronicmaterials e.g. MoS2, may also be used. The semiconductor layer may bedeposited by a range of known techniques including PVD, CVD or ALD,printing (e.g. inkjet, aerosol-jet, gravure, flexo), spin-coating orother coating methods (such as doctor-blade, slot-die), or sol-gel andspray pyrolysis.

Electrode materials will be chosen to match the electronic properties ofthe semiconductor layer, for example to ensure efficient injection intothe thin-film device. A range of metals are appropriate, such as Ni, Ti,Au, Mo, Al, or multi-layers of metals such as Ni/Au, Ti/Au, Ni/Pd,Ti/Al, Ag. conducting metal-oxides such as ITO, IZO, ZnO, AZO may alsobe appropriate choices or common electrode materials such as titaniumnitride (TiN). As deposition processes mature 2D materials such asgraphene or modified graphenes may be used. The choice of electrode mustalso be compatible with processing on the semiconductor layer withoutdeleteriously affecting the desired properties. A range of depositionprocesses may be used including PVD, CVD or ALD, and other thin-filmtechniques well-known.

A range of low-k dielectric materials are well known within theelectronics and semiconductor industry. These include inorganicmaterials, such as spin-on glass, and organic materials includingpolymers which are solution-processed (e.g. BCB, polyimide),sublimed/evaporated (parylene) or deposited by CVD. A typical k-valuewould range from 2.5 to 4. The choice of low-k material needs to becompatible with the underlying electrode material to ensure it can bepatterned at the same time whilst minimising the isotropic (lateral)etching of the low-k material. Any lateral etching of the low-k materialwill introduce additional parasitic capacitance where the gate electrodeoverlaps with the source/drain electrode only across the high-kdielectric dielectric.

Referring now to FIG. 3, this illustrates steps in another methodembodying the invention. In step A, a carrier 6 is provided. In step B,a substrate 7 is formed (e.g. deposited, printed, or otherwise provided)on a carrier. In step C a barrier layer 8 is formed (e.g. deposited) onthe substrate. In step D, an insulator layer 9 is formed (e.g.deposited) on the barrier layer.

In step 3E the semiconductor layer or body is formed (e.g. deposited) onthe insulator layer, and then in step F the semiconductor layer or body1 is patterned. It will be appreciated that in alternative methodsembodying the invention steps E and F may be replaced by a single stepof selective deposition or printing of a patterned semiconductor layer.

In step G a conductor layer or body is formed (e.g. deposited) on thepatterned semiconductor layer 1.

In step H a layer or body of second dielectric material (e.g. low-Kmaterial) is formed (e.g. deposited) over the conductor layer 2. Then,in step I, the second dielectric material layer is patterned. It will beappreciated that steps H and I could be replaced by a single step ofselective deposition or printing of a patterned layer of seconddielectric material.

In step 3J, using the portions 31 and 32 of low-K material as masks, theconductor layer 2 is patterned to leave first and second terminals 21and 22 covering underlying first and second portions 11, 12 respectivelyof the semiconductor layer 1.

In step 3K, a gate dielectric layer 4 of first dielectric material isformed (e.g. deposited) over the underlying structure, and then in step3L is patterned to leave a portion 43 covering the channel, a portion 41overlapping part of the first terminal, a second portion 42 overlappingpart of the second terminal 12, further portions 40 covering outlyingsurfaces of the layer 9, and windows 310 and 320 leaving exposed partsof the upper surfaces of the portions 31 and 32 of low-K material.

It will be appreciated that in certain embodiments steps K and L couldbe replaced by a single step of selectively depositing or printing apatterned gate dielectric layer.

In step 3M further patterning is performed, removing the exposedportions of the low-K material and exposing underlying surfaces of thefirst and second terminals 21, 22.

In step 3N a gate layer 5 of conductive material is formed (e.g.deposited) over the underlying structure. Then, in step 3O, the gatelayer is patterned to form gaps or windows 550 separating the conductivematerial forming the gate 50 from further portions of conductivematerial 54 and 55. The portion of conductive material 54 partiallyfills the window 310 formed in step 3M, and forms a via (i.e. aconnection) to the underlying source terminal 21. Similarly, a portion55 at least partly fills the void 320 and forms a via connecting to theunderlying drain terminal 22. The gate 50 has a channel portion 53covering the channel portion 13, a first overlapping portion 51overlapping part of the source 21, and a second overlapping portion 52overlapping part of the drain 22. The presence of the low-K materialunderneath each of these overlapping portions 51, 52 substantiallyreduces the parasitic capacitance of the device.

It will be appreciated, that in certain alternative embodiments steps 3Nand 3O could instead be replaced by a single step of selectivelydepositing or printing a patterned gate conductor layer.

Referring now to FIG. 4, this illustrates steps in a technique suitablefor patterning any layer, or multilayer structure, in methods embodyingthe invention. The layer to be patterned is labelled 1000. That layer1000 is supported by a supporting layer, structure, or body 96 (whichmay take any suitable form, to suit requirements). In step 4 a a mask1010 is formed (e.g. deposited or printed) on or over the layer to bepatterned 1000. Next, in step 4 b, exposed (i.e. unmasked) portions ofthe layer 1000 are removed by any suitable technique (e.g. etching) topattern the layer 1000. Finally, in step 4 c, the mask 1010 is removed,leaving the patterned layer 1001 still supported by 96.

FIG. 5 illustrates an alternative patterning technique, which may beused in embodiments of the invention. Again, the layer 1000 to bepatterned is provided on the support 96. As shown in FIG. 5a , a layer,body, or covering of resist material 1020 is formed over the layer to bepatterned, with depressions 1021 in the upper surface of the resistlayer defining the pattern. Between depressions 1021 are relativelythicker portions 1023 of the resist material. Those depressions may beformed by a variety of techniques, including imprinting, for example. Instep 5 b the depressions 1021 are developed by removing resist material(e.g. by etching) to an extent that portions of underlying layer 1000are exposed, and then those exposed portions are also removed. In step 5c the remaining resist material is removed, to leave patterned layer1001 on the support 96.

Additionally, or alternatively, patterned layers may be provided byprinting (i.e. a patterned layer may be formed directly by printing),thereby avoiding the need to pattern after deposition (of an unpatternedlayer/body).

Referring now to FIG. 6, this shows another transistor embodying theinvention.

FIG. 6 shows some overlap of gate electrode to source/drain layer wherethere is no low-k dielectric. In other words, the portion or region 31of low-k material does not entirely cover the source terminal 21, nordoes the portion 32 completely cover the drain terminal 22. As thisoverlap increases the shielding effect of the low-k dielectric spacerlayer will be reduced, and the overall parasitic capacitance increased.However, if the low k material covers the majority of the source anddrain terminals (or at least the portions of them overlapped by thegate) then the overall parasitic capacitance may be kept acceptably low.

The gate dielectric material could be chosen from inorganic or organic.This material will be chosen to match the semiconductor material. Ametal-oxide material, such as Al2O3, may be suitable for a metal-oxidesemiconductor, such as IGZO. A range of deposition processes may be usedincluding PVD, CVD or ALD, and other thin-film techniques well-known.The gate dielectric material will typically be a high-k dielectricmaterial with k>4. Other examples include Ta2O5, HfO2, PVDF, BaTiO3.

The gate electrode materials can be selected from a range of conductivematerials including metals such as Ni, Ti, Au, Mo, Al, or multi-layersof metals such as Ni/Au, Ti/Au, Ni/Pd, Ti/AI, Ag; conductingmetal-oxides such as ITO, IZO, ZnO, AZO or other common electrodematerials such as titanium nitride (TiN). A range of depositionprocesses may be used including PVD, CVD or ALD, and other thin-filmtechniques well-known.

Referring now to FIG. 7, this shows part of a circuit embodying theinvention, and incorporating a transistor embodying the invention. Thetransistor 100 is generally as described with respect to FIG. 2.Additionally, the layer of conductor material 2 comprises a furtherportion 24 extending from the source terminal/region 21, and the low-klayer/body comprises a further portion 34, initially formed to cover theentire portion 24. Similarly, the first dielectric material layer/bodycomprises a further portion 44, initially formed to cover the entireportion 34. In one of its manufacturing steps, a hole through theportions 44 and 34 has been formed, to expose part of the upper surfaceof the portion 24 of conductor material. Then, when the layer of gatematerial has been formed, that conductive material 5 has also at leastpartially filled the hole to form a conductive via, making electricalconnection to the underlying portion 24 and hence to the source terminal21. Subsequent processing has then patterned the second layer ofconductor material 5 to separate the portion forming the via 54 from thegate electrode 50 itself.

In more detail, a method suitable for manufacturing the structure shownin FIG. 7 is as follows:

Process:

(i) Prepare substrate 7 on carrier 6

(ii) Deposit barrier 8 (optional)

(iii) Deposit insulator 9

(iv) Deposit semiconductor 1 (and optionally pattern)

(v) Deposit source-drain electrode layer 2

(vi) Deposit low-k dielectric layer 3

(vii) Pattern low-k dielectric layer (forming gate mask) The gate maskopens up a window above the semiconductor channel 13 to form gate areawith self-aligned channel

(viii) Pattern source-drain electrode layer (to form source 21, drain22, and further 24 regions)

(ix) Deposit gate dielectric layer 4

(x) Pattern gate dielectric layer (forming window through to region 34to define position of via

(xi) Pattern low-k dielectric layer (forming via mask). The via maskopens up a window above first metallisation layer (SD) to form via. Thisis disconnected from the rest of the gate layer by patterning. Thislayer could alternatively be selectively printed.

(xii) Deposit gate layer 5

(xiii) Pattern gate layer

Referring now to FIG. 8, this shows another transistor embodying theinvention.

An insulating substrate 7 is provided onto which a layer ofsemiconductor 1 is deposited. A conductor layer 2 is deposited ontolayer 1, followed by a layer of low-k dielectric material 3. Layers 2and 3 are patterned, for example using plasma-etch processing, to createwindow above semiconductor layer 1, creating segments 21, 22 and 31, 32in layers 2 and 3, respectively. A further high-k dielectric material 4is deposited onto the substrate covering exposed areas of layers 1, 2,and 3. A further conductor layer 5 is then deposited. The finalstructure is a top-contact, top-gate thin-film transistor comprisinginsulating substrate 7, semiconductor layer 1, source electrode 21,drain electrode 22, gate dielectric layer 4 and gate layer 5. Layer 3provides a spacer or interlayer dielectric (ILD) between conductivelayers 2 and 5. In doing so this reduces the “Miller Capacitance” of thedevice, well known in thin-film electronics.

In a further embodiment, the insulating substrate 7 is 200 umpolyethylene terephthalate (PET) and a 50 nm layer of indium galliumzinc oxide (IGZO) is deposited by RF magnetron sputtering. A 100 nmlayer of molybdenum (layer 2) is deposited by DC sputtering, followed bydeposition of a 300 nm thick layer of parylene (layer 3). PhotoresistS1805 (1.2 um) is spin-coated onto the substrate, soft-baked and exposedthrough a photomask, hard-baked and then developed to expose a windowonto the layer of parylene. The exposed parylene is removed using oxygen(O2) plasma to expose the top-surface of molybdenum. The exposedmolybdenum is then removed using a CF4/O2 plasma to expose thetop-surface of IGZO. The photoresist is then removed by flood-exposure(UV) and develop. A 100 nm layer of Al2O3 (layer 4) is deposited byatomic-layer deposition (ALD), followed by a 100 nm layer of molybdenum(layer 5) deposited by DC sputtering to provide the gate electrode.

FIG. 9 shows a further transistor embodying the invention, in particulara top contact configured metal oxide thin film transistor (TFT).Materials and dimensions are shown on the figure. The TFT DriverDimensions were: L=1 um, 0.5 um, W=50 um. In this example the gatedielectric is alumina; dielectric constant 8, thickness 50 nm. The low Kdielectric is a material with dielectric constant 4, thickness 300 nm.Length of overlap, Lov, approximately Lov=3 um. Calculations haveindicated that such embodiments may exhibit TFT speeds approximately 2to 6 times faster than equivalent TFTs without the low k materialpresent.

It will be appreciated from the above description that certain methodsembodying the invention provide a new process that enables“self-aligned” gate transistors with low miller capacitance to bemanufactured. This process may use an in-situ etch-mask which is low-k(e.g. k<4) to spatially separate the gate metal from the SD layer. Thisavoids the need for reverse-side exposure.

The process may comprise the steps:

(i) Deposit semiconductor (optionally pattern)

(ii) Deposit SD layer

(iii) Deposit intermetal dielectric (IMDO)

(iv) Pattern IMDO+SD

(v) Deposit gate dielectric layer

(vi) Pattern gate dielectric

(vii) Optionally use gate dielectric layer as hard-mask to pattern IMDO(to create via to SD layer)

(viii) Deposit gate metal layer

(ix) Pattern gate metal layer

In certain embodiments, the gate dielectric is patterned and then usedas a mask to pattern the low-K regions covering the S and D terminals tocreate via holes through to those terminals. The gate metal layer maythen be formed, connecting to the SD layer by creating one or more vias.Subsequent patterning of the gate metal layer may then define whetherthese vias are connected or not. The vias are there to enableupper-level interconnects to be routed.

1. A transistor comprising: a layer (or other body) of semiconductormaterial comprising a first portion, a second portion, and a thirdportion connecting the first portion to the second portion and providinga semiconductive channel between the first portion and the secondportion; a conductive first terminal covering and in electrical contactwith said first portion of the layer of semiconductor material; aconductive second terminal covering and in electrical contact with saidsecond portion of the layer of semiconductor material; a conductive gateterminal comprising a first overlapping portion covering at least partof the first terminal, and a channel portion covering the third portionof the layer of semiconductor material; and a layer (or other body) of afirst dielectric material, having a first dielectric constant, arrangedbetween the first overlapping portion and the first terminal, andbetween the channel portion of the gate terminal and the third portionof the layer of semiconductor material, characterised in that thetransistor further comprises a layer (or other body) of a seconddielectric material having a second dielectric constant, said seconddielectric constant being lower than said first dielectric constant,said layer of said second dielectric material being arranged between atleast part of the first overlapping portion and the first terminal,whereby said at least part of the first overlapping portion of the gateterminal is separated from the first terminal by said layer of firstdielectric material and said layer of second dielectric material. 2-31.(canceled)